1. Field of the Invention
The present invention relates to an differential charge pump circuit, and more particularly, to an differential charge pump circuit with a current drive property of not depending on the output potential difference.
2. Background Art
Conventional differential charge pump circuits are structured as shown in FIG. 7. That is, along with connecting a first current path 1 including current sources 11 and 12 and a second current path 2 including current sources 21 and 22 between a power source VDD and a ground GND, a differential pair 3 is formed; and a DOWN signal circuit 5 and an UP signal circuit 7, which are connected to a constant current source 4, are connected to a positive node 6 of the first current path 1 and to a negative node 8 of the second current path 2 respectively.
In a structure as mentioned above, the UP/DOWN signals are converted to current signals and passed on to the differential pair 3; by extracting the current from the two current paths 1 and 2, the current which flows through one of the two current paths is changed relatively to the other current path and a differential current is generated; and conversion from voltage signals to current signals is carried out. In the case where the electric potentials of the positive node 6 of the first current path and the electric potential of the negative node 8 of the second current path are not equal during operation, the drain voltages of the transistor (graphic representation not given) which comprise the current sources 11 and 12 become different from each other, and an imbalance between the currents of the current sources 11 and 12, which are the opposite current sources in the first and second current paths 1 and 2, occurs.
The imbalance in the current is caused by the dependence of the current characteristics of the saturated area of the MOS transistor on the drain current. The relation between the drain current ID of the transistor, the gate voltage VGS, the drain voltage VDS, and the threshold voltage VTH may be explained by the undermentioned equation (for example, refer to David Johns & Ken Martin, “Analog Integrated Circuit Design”, published 1997 by John Wiley & Sons, Inc.):ID=KO(VGS−VTH)2[1+λ(VDS−(VGS−VTH))]
That is, since the drain current value has the characteristic of depending on the drain voltage, to explain referring to FIG. 8 which shows the detailed structure of each of the current sources in FIG. 7, in the case where there is a difference between the electric potentials of the output nodes 6 and 8 of the differential pair 3, the current values of the current sources 11 and 12, and the current sources 12 and 22, which are the opposite current sources in the first and second current paths 1 and 2, become respectively different. In the drawing, the broad arrows indicate that the current is large; and the thin arrows indicate that the current is small.
If the electric potential of the positive node 6 is higher than the electric potential of the negative node 8, between the NMOS current sources 12 and 22, current flows more through the first current path 1 of the positive node 6 (to which the positive node 6 belongs).
In this drawing, the constant-current property is improved by forming the two MOS transistors of both the PMOS side and the NMOS side in a cascode configuration; however, actually, a certain amount of electric potential difference remains between the nodes X and Y, and between the nodes Z and W. In the case where the cascode configuration is not employed, it may be considered that the electric potential differences would become even larger.
On the other hand, as for the PMOS current sources 11 and 21, since the electric potential difference between the drain and the source is larger in the second current path 2 of the negative node 8 (to which the negative node 8 belongs) than in the first current path 1, current flows more in the current source of the second current path 2. Accordingly, taking both the NMOS and the PMOS into consideration, more current flows through the positive node 6 towards the GND (i.e., the NMOS current source 12 carries more current), and more current flows through the negative node 8 towards the VDD (i.e., the PMOS current source 21 carries more current). As a result of this, in the case where there is a difference in the output potentials of the differential pair 3, the charge pump characteristics depend largely on the electric potential difference.
As a result of this, for example, in a case where the above-mentioned differential charge pump circuit is applied to a charge pump circuit of a PLL circuit, the phase comparison characteristic changes according to the output potential difference of the charge pump circuit.
Generally, the phase comparator of a PLL circuit transmits a pulse signal according to the phase difference between the reference clock (or the data) and the feedback clock to the charge pump circuit; and the charge pump circuit outputs a current value according to the pulse signal thereof. Ideally, the phase difference and the current amount flowing through the charge pump circuit should correspond one-to-one regardless of the output potential of the charge pump circuit.
FIG. 9 is a graph showing the result from circuit-simulating the phase comparison characteristic of the PLL circuit when the output potential difference of the differential charge pump circuit is varied. The horizontal axis represents the phase difference between the reference clock (or the data) and the feedback clock expressed by time; and the vertical axis shows the average value of the current flowing through the charge pump circuit in each of the phases. When the average current of the charge pump circuit is zero, the PLL circuit becomes locked. Accordingly, the phase difference at that time shows the phase error (i.e., the offset of the reference clock (or the data) and of the feedback clock) when the PLL circuit is locked.
Since the current value of the constant current source of the conventional differential charge pump circuit differs depending on the output potential difference of the charge pump as mentioned above, the phase error at a locked time when the output potential difference of the charge pump circuit is varied changes according to the output potential difference of the charge pump circuit. In the simulation shown in FIG. 9, at the variation of ±0.1 V of the output potential difference (electric potential of positive node minus electric potential of negative node), the phase error change is about 5 ps.
Since the conventional differential charge pump circuit is structured as mentioned above, the precision of the phase adjustment of the PLL circuit deteriorates due to the phase error change shown in the simulation in FIG. 9, and this creates a great problem in the high-speed interface DLL (Delay-Locked-Loop: phase adjustment loop) circuit, or a CDR (Clock and Data Recovery) circuit, which necessitate high-precision phase adjustment.